1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to various embodiments of a capacitor structure positioned at the device level of an integrated circuit product, and various methods of making such capacitors and products.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements, such as transistors, capacitors, resistors, etc., to be formed on a given chip area according to a specified circuit layout. During the fabrication of complex integrated circuits using, for instance, MOS (Metal-Oxide-Semiconductor) technology, millions of transistors, e.g., N-channel transistors (NFETs) and/or P-channel transistors (PFETs), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically includes doped source and drain regions that are formed in a semiconducting substrate and separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
FIG. 1 is a simplified view of an illustrative prior art transistor device 10 that is formed above a semiconducting substrate 12. The device 10 is formed in and above an active region 13 that is defined in the substrate 10 by an illustrative trench isolation structure 14. The transistor 10 includes a schematically depicted gate electrode structure 20 (that typically includes a gate insulation layer 20A and a gate electrode 20B), a plurality of source/drain regions 22, sidewall spacers 26, and a plurality of metal silicide regions 24. Also depicted in FIG. 1 are a plurality of conductive contact structures that are conductively coupled to the source/drain regions 22 and the gate electrode 20B. Such conductive contact structures are formed in layers of insulating material 29A, 29B, e.g., silicon dioxide, and the conductive contact structures may take a variety of forms. In the depicted example, the source/drain regions 22 are contacted by so-called source/drain interconnects 28 that contact so-called trench silicide regions (not shown) in the source/drain regions 22. Illustrative source/drain contacts 30 contact the source/drain interconnects 28. The gate electrode 20B is electrically contacted by a gate contact 34. The illustrative source/drain regions 22 depicted in FIG. 1 have an upper surface that is approximately level with the upper surface of the substrate 12. Transistors with so-called raised source/drain regions are also known in the art.
The various structures and regions of the transistor 10 depicted in FIG. 1 may be formed by performing well-known semiconductor manufacturing processes. For example, the gate structure 20 may be formed by depositing various layers of material and thereafter performing one or more etching process to define the basic layer stack of the gate structure 20. The sidewall spacers 26 may be formed by depositing a layer of spacer material, such as silicon nitride, and thereafter performing an anisotropic etching process on the layer of spacer material. The source/drain regions 22 may be formed using known ion implantation techniques using the appropriate dopant materials, i.e., N-type dopants or P-type dopants, depending upon the device under construction. The metal silicide regions 24 may be formed by performing traditional silicidation processes, i.e., depositing a layer of refractory metal, performing a heating process causing the refractory metal to react with underlying silicon-containing material, removing unreacted portions of the layer of refractory metal (e.g., nickel, platinum or combinations thereof), followed perhaps by performing an additional heating process. The conductive structures 28, 30, 34 that provide electrical connection to the source/drain regions 22 and the gate electrode 20B may be formed using well-known processes.
Although not depicted in FIG. 1, a plurality of so-called metallization layers are formed above the device 10, e.g., 7-14 metallization layers. The metallization layers are comprised of conductive lines and/or conductive vias that are positioned in a layer of insulating material. In general, the conductive lines and vias in the metallization layers constitute the “wiring” pattern that connects various semiconductor devices, e.g., transistors, capacitors, resistors, together in a desired configuration to create a working integrated circuit product. As to terminology, the transistor 10 is generally formed at what is known as the “device level” of an integrated circuit product, as that is the level at which discrete devices, e.g., transistors, resistors, are formed in the semiconducting substrate 10. So-called “front end-of-line” (“FEOL”) processes generally refer to all to the processing from wafer start through final contact window processing. FEOL processes include formation of the gate structure 20, the isolation region 14, the source/drain regions 22, etc., including the activation anneal of the source/drain regions 22. So-called “back end-of-line” (“BEOL”) processes generally refer to the process steps after formation of the conductive contact structures shown in FIG. 1 through completion of the wafer prior to wafer electrical test, i.e., BEOL processing is typically considered to begin with the formation of the first general “wiring” layer for the device, the so-called “metal-1” layer, formed on the wafer.
In modern, ultra-high density integrated circuits, device features have been steadily decreased in size to enhance the performance of the semiconductor device and the overall functionality of the circuit. For example, the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 20-50 nm and further scaling (reduction in size) is anticipated in the future. This ongoing and continuing decrease in the channel length of transistor devices has improved the operating speed of the transistors and integrated circuits that are formed using such transistors. However, there are certain problems that arise with the ongoing shrinkage of feature sizes that may at least partially offset the advantages obtained by such feature size reduction. For example, as the channel length is decreased, the pitch between adjacent transistors likewise decreases, thereby increasing the density of transistors per unit area. This scaling also limits the size of the conductive contact elements and structures, which has the effect of increasing their electrical resistance. In general, the reduction in feature size and increased packing density makes everything more crowded on modern integrated circuit devices, at both the device level and within the various metallization layers.
Improving the functionality and performance capability of various metallization systems has also become an important aspect of designing modern semiconductor devices. One example of such improvements is reflected in the increased use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” dielectric materials (materials having a dielectric constant less than about 3) in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior metallization systems that used tungsten or aluminum for the conductive lines and vias. The use of low-k dielectric materials tends to improve the signal-to-noise ratio (S/N ratio) by reducing crosstalk as compared to other dielectric materials with higher dielectric constants. However, the use of such low-k dielectric materials may be problematic as they tend to be less resistant to metal migration and tend to be weaker mechanically as compared to some other dielectric materials with higher k values.
Additionally, in many products, various capacitor structures (not shown in FIG. 1) are formed above the transistor device 10 in the various BEOL metallization layers. Such on-chip capacitors are critical components in modern integrated circuit products. Such capacitors are used for a variety of purposes, e.g., coupling/decoupling, bypass and capacitive matching, etc. The capacitors typically come in three distinct forms: MIMCAPs (metal-insulator-metal capacitors), MCAPs (metal capacitors) and VNCAPs (vertical natural capacitors). MIMCAPs are formed by parallel plates of metal at or near the very top of the BEOL metallization layers. MCAPs and VNCAPs are formed by various different types of comb structures that are replicated at multiple levels of the metallization layers. VNCAPs differ from MCAPs in that VNCAPs include connecting vias in the metal comb stacks which results in the VNCAPs having a greater capacitance density.
As noted previously, all of the above-identified capacitor structures are formed in the BEOL metallization layers, where lower k value dielectric materials are normally used to reduce parasitic capacitance and signal-to-noise ratios (S/N ratio). Unfortunately, such lower-k dielectric materials are less than ideal as it relates to the ability to store charge in the capacitor devices. The amount of charge that a capacitor may store is directly related to dielectric constant (‘k”) of the insulating material used in making the capacitors. Thus, while the use of low-k dielectric materials may reduce parasitic capacitance and signal-to-noise ratios, such low-k material causes problems as it relates to the formation of capacitor structures. For example, the effect of using such low-k materials in the BEOL metallization layers is that the physical size of the capacitor structures formed in such low-k material layers must be increased, as compared to the size of such capacitors if a dielectric material with a higher k-value were used in the BEOL metallization layers. However, the use of a higher k-value dielectric material would offset the advantages achieved by using low-k material in the BEOL metallization layers, such as reducing parasitic capacitance and signal-to-noise ratios, as discussed above.
The present disclosure relates to methods and devices for avoiding or at least reducing the effects of one or more of the problems identified above.